J4 Logic Field Processor
Powering brain-scale intelligence. Marziani Labs™ has entered a strategic partnership with J4.AI to help bring Jeff Glickman’s patent-pending J4 Stochastic Learning architecture and Logic Field Processor (LFP) silicon platform to market — supporting fundraising, platform commercialization, and go-to-market execution alongside J4, who originated and holds the underlying intellectual property.
- Dedicated silicon for J4 Stochastic Learning
- Massive computation at the edge
- Lower power and cooling burden in data centers
The J4 Logic Field Processor
The J4 Logic Field Processor
The Objective: Brain-Scale AI
J4.AI states its purpose in a single sentence: build brain-scale AI — a machine, sometimes called embodied AI, that is as capable as a person or more so. Every program at the company, the Logic Field Processor included, exists to close one part of that gap.
The benchmark is biological, and it is unforgiving. A human brain weighs three to four pounds and runs on roughly twelve watts. Assemble every supercomputer and every cloud data center on earth and the combined result still cannot fold a basket of laundry. That gap — not model quality — is the problem J4 has organized itself around.
Reaching that envelope requires solving four distinct problems. J4’s roadmap is organized around them, and the LFP is the answer to the second.
1 · The Computation Gap
Roughly nine orders of magnitude separate current computing from the brain’s effective throughput. Incremental accelerator gains do not close a gap of that size.
2 · Energy and Heat
Power draw and the heat it produces. Today’s answer is water cooling — a scarce resource that AI data centers are already competing for against municipal and agricultural demand.
3 · Combinatorial Optimization
The class of problems humans solve continuously and without effort, and that no computer solves exactly. Covered in Section 10.
4 · Thought, Not Transformation
Large language models transform language. J4’s position is that this is a reasonable language faculty for a larger system, but it is not thinking, and it does not close the gap on its own.
“They allow you to transform language, but they don’t actually think, and they don’t understand. As a language center for a larger AI system it’s a reasonable solution — but it’s not thought.”
— Jeff Glickman, founder & inventor, J4.AI, on large language models · August 2026
This is not a new program. J4 reports work on the problem beginning in 2000, a working understanding of the solution in 2005, and a completed prototype in 2010 — with the resulting system in continuous operation since.
Generative AI Has Hit a Physical Limit
The limiting factors for AI are shifting from algorithms to infrastructure: power, cooling, water, grid access, and distance from the user.
The infrastructure behind the algorithm
Not Another Accelerator for the Same Generative AI Workload
J4 pairs a different learning method with a purpose-built processor.
J4 Stochastic Learning + Logic Field Processor
A new performance curve: useful predictions per joule.
Sources: IEA, Berkeley Lab, IDC.
The Problem: AI Is Consuming the Operating Envelope
Generative AI infrastructure is increasingly constrained by what can be powered, cooled, connected, permitted, and built.
Sources: IEA, Berkeley Lab, ARPA-E.
The Cloud Is Too Far From the Edge
Latency-sensitive AI must make decisions where the data is created — at machines, sensors, vehicles, devices, and facilities.
Computation at the point of decision
Cloud AI
Centralized · connected · distant
Edge AI
Local · autonomous · real-time
Constraints of the Cloud Model
- Network round-trip latency
- Bandwidth and transfer cost
- Privacy and data-residency exposure
- Loss of autonomy when disconnected
Current Accelerators Optimize Generative AI
GPUs, TPUs, NPUs, and cloud ASICs are extraordinary — but they mostly accelerate the same dominant paradigm.
Dominant Workload
Matrix and tensor operations · deep-learning frameworks · high-bandwidth memory movement · centralized scale-out processing
J4 Alternative
Stochastic partial differences · relationship discovery fabric · fitness-based pruning · edge-to-data-center processing
August 2026 update — an interim GPU path. Stochastic learning is not naturally suited to GPU execution, and J4.AI has been direct about that. The team now reports a recently developed middle-ground implementation that lets stochastic learning run reasonably on NVIDIA GPUs — a bridge for organizations that want to evaluate the method on infrastructure they have already invested in, while the LFP remains the purpose-built accelerator the program’s economics are designed around.
Sources: Google TPU docs, AWS Trainium/Inferentia docs, Intel Loihi 2 docs.
J4 Stochastic Learning Changes the Boundaries
Instead of training only through repeated tensor operations, J4 Stochastic Learning searches for predictive stochastic relationships among variables.
Candidate relationships converging to a prediction
The method grew out of J4.AI’s long-term research goal: brain-scale AI — intelligence that does what a human brain does, in something like a brain’s volume and power envelope. By the team’s own assessment the industry is off by at least eight orders of magnitude, and the biology keeps getting harder: J4 points to modern brain atlases that now catalogue more than 3,300 distinct cell classes, and to structures once dismissed as scaffolding that turn out to participate in processing. Stochastic learning is one problem solved on that road — a learning method that spends radically less energy per useful prediction.
The measured shape of the advantage. J4 characterises stochastic learning as running three to four orders of magnitude more efficiently than an artificial neural network — faster and at lower power dissipation simultaneously, rather than trading one for the other. A consequence that matters at data-center scale: the method requires no water cooling. Against the brain-scale target, the team places that first step at roughly 1,000× to 10,000× closer.
“We discovered a way to process data with a lot less energy than an artificial neural network — at least three orders of magnitude less, probably closer to four. That’s stochastic learning, and we’ve filed patents for it.”
— Jeff Glickman, founder & inventor, J4.AI · August 2026. Independent validation of the energy claim is the first milestone of the financing plan (Section 11).
Source: WO2024258795A1 / US20240419998A1.
Rewriting the Neuron: Where the Efficiency Comes From
The energy advantage is not an optimization of the artificial neural network. It comes from J4’s position that the standard mathematical model of a neuron is simply wrong, and that a more faithful model turns out to be dramatically cheaper to compute.
The problem with the model. Modern brain atlases catalogue on the order of 3,300 distinct classes of neuron. Artificial neural networks represent all of them with one equation. Recent findings compound the mismatch: computation appears to occur in axons as well as dendrites, meaning the single model in use is not a simplification of biology so much as a different thing altogether.
What biology actually does. Neurons are spiking systems. What carries information is not the absolute amplitude of a signal but the timing — when potentiation arrives on an axon, and when the neuron emits to the next neuron in turn.
The reformulation. J4 rewrote the neuron as a set of stochastic partial differential equations. That branch of mathematics rests on Norbert Wiener’s 1920s work on Brownian motion and was built out by Kiyosi Itō in Japan in the 1940s. It was not widely absorbed outside pure mathematics until the 1980s and is still taught at relatively few universities — which is part of why the approach has stayed uncontested.
Why it collapses. Solving those equations directly would be expensive. Examining the roots of their solutions is not. At the roots, the required computation reduces to a very small number of operations, and those operations devolve essentially into comparisons: is one potentiation larger than another arriving at the same moment, and if they do not arrive together, they are separable events. Comparisons are cheap in silicon. That is stochastic learning.
Artificial Neural Network
One neuron model · amplitude-weighted · dense matrix and tensor arithmetic · energy scales with parameter count
J4 Stochastic Learning
Spike-timing formulation · stochastic partial differential equations · solved at the roots · computation reduces largely to comparisons
Evidence by use, not by claim. J4 runs the method against live market data, where the arrival rate of ticks sets a hard floor on how slow a system is allowed to be. In 2015 the computation was heavy enough to produce one prediction per day. That moved to hourly, then per minute, then per second. Today J4 reports calculating at tick rate — as fast as market data arrives, in real time.
Source: J4.AI technical briefing, August 2026. Independent validation of the energy claim is the first milestone of the financing plan (Section 11).
LFP Turns J4 Stochastic Learning Into Silicon
The Logic Field Processor is a proposed compute fabric specialized for relationship generation, objective scoring, and pruning.
The clearest analogy, and its limit. The LFP occupies the same position for stochastic learning that an NVIDIA GPU occupies for artificial neural networks — the dedicated silicon that makes the method economically practical at scale. The analogy stops there. A GPU cannot run stochastic learning well, because stochastic learning does not compute in matrix and tensor operations. It resolves into comparisons over spike-timing relationships (Section 07), and that shape of work needs a fabric designed for it.
Why the chip is the difference between close and there. Stochastic learning in software delivers three to four orders of magnitude. J4 projects that dedicated silicon contributes roughly three orders of magnitude more. Stacked, those two multipliers are what move brain-scale AI from a distant target to a reachable one — which is why the LFP, and not the learning method alone, is what this financing is built around.
Projected multipliers stated by J4.AI, August 2026. The first independent reproduction of the energy result is the opening milestone of the financing plan (Section 11).
Source: patent application implementation language.
Why Classical Silicon, Not Quantum
The LFP is a room-temperature classical processor built on conventional silicon and conventional manufacturing. That is a deliberate choice against the prevailing direction of frontier compute investment, and J4 grounds it in a specific physical argument rather than a preference.
First, a distinction. J4 separates quantum communications from quantum computing and treats them very differently. On secure and quasi-secure communications built with quantum systems, the team expresses no doubt. The skepticism is directed only at large-scale quantum computation.
The scaling argument. Useful quantum computation emerges somewhere in the range of millions of entangled qubits. Working systems today are built with dozens to a hundred, arguably a thousand. The distance is not incremental.
The noise floor. Any physical system operates above absolute zero, and absolute zero is not achievable. Above it, every qubit emits 1/f noise. Entangle a million qubits and each one must withstand the 1/f noise contributed by every other qubit in the system. The larger the entangled system, the higher the noise threshold each individual qubit has to survive — and the requirement becomes unmanageable quickly.
The trade with no solution. The only lever against that noise is temperature, and the lever has a floor. J4’s assessment is that no saddle point exists where a large-scale quantum system is simultaneously cold enough to be coherent and large enough to be useful. Absent that point, the company builds in silicon at room temperature.
Quantum Communications
J4 position: viable. Secure and quasi-secure communication systems built on quantum effects are achievable.
Quantum Computation at Scale
J4 position: unresolved. The entanglement-versus-noise trade has no demonstrated operating point at the scale that useful computation requires.
There is a second reason the choice matters commercially. Much of the economic case for quantum computing rests on problems classical machines are believed unable to solve efficiently — principally the combinatorial class described in Section 10. J4’s research position is that this class may be classically solvable. If that proves correct, the strongest argument for quantum computing weakens considerably, and it weakens in favor of the architecture the LFP already implements.
This assessment comes from inside the field rather than outside it: the first course Glickman taught covered Josephson junctions, the superconducting structures used as quantum gates today. The position is presented here as J4’s stated technical judgment, not as settled consensus — substantial and well-funded programs disagree with it.
Source: J4.AI technical briefing, August 2026.
The Second Problem: Combinatorial Optimization
Efficient computation is necessary for brain-scale AI but not sufficient. The second unsolved problem on J4’s roadmap is combinatorial optimization — and unlike the first, it carries immediate commercial revenue independent of the silicon.
The canonical form is the traveling salesman problem: given a set of cities, what is the shortest route that visits each exactly once? There is no known efficient exact solution. It sits at the root of computation itself, and the Clay Mathematics Institute maintains a prize for the underlying question.
The same problem appears throughout industry wearing different clothes. Which aircraft goes to which gate. How to lay out a bus network and its stops. What order to drill holes in a printed circuit board. Each instance has a direct economic consequence.
What the gap costs. Every large logistics operator runs on approximations. Approximation gets close, but it typically concedes a few percent or more against the true optimum. At the scale of a UPS, a FedEx, a Walmart, or a PepsiCo, a few percent of logistics spend is measured in billions of dollars a year — per company. The money is not lost to inefficiency in execution; it is lost because the exact answer cannot currently be computed.
Why it belongs on the brain-scale roadmap. A person holds a conversation, folds laundry, and tracks what is on a screen simultaneously, without noticing the effort. That is continuous combinatorial resolution. Every computer on earth put together does not do it. A machine that cannot solve this class of problem does not reach brain scale, regardless of how efficiently it computes.
Where J4 stands. The company runs an active research effort on combinatorial optimization and reports results it considers good, with work continuing toward a conclusion. Its stated position — contrarian to most of the field — is that P may equal NP. This remains unproven and is presented here as a research direction rather than an established result. The commercial intent is to expose the capability as a public API, sold into logistics, routing, and scheduling.
Source: J4.AI technical briefing, August 2026. Company positions on P vs NP are unproven research claims.
The Round Funds the Proof
The investment case depends on independently reproducing a step-function gain in useful predictions per joule — targeting 1,000×+ on selected workloads versus equivalent task quality.
1 · Independent Validation
Energy + task quality
2 · FPGA Scale-Out
Kernel parallelism
3 · First Silicon
Thermal + system proof
A Product Family — Not a Single Chip
The first product is not merely silicon. It is a platform that lets customers evaluate, program, deploy, and scale Stochastic Learning.
SDK to data center — one product family
Market Opportunity: Focused Entry Into a Huge Market
J4 does not need to replace every accelerator. It needs to win the workloads where power, cooling, latency, or autonomy is the bottleneck.
Where watts and milliseconds matter
Illustrative Year 5 Target
$650M — approximately 0.23% of the 2026 intelligent datacenter silicon segment.
Sources: IDC AI infrastructure and semiconductor forecasts, SpaceX IPO prospectus, Morgan Stanley report.
Go-to-Market: Sell Where Watts and Milliseconds Matter
Start with design partners whose workloads have high compute cost, clear objective functions, and power or latency constraints.
Business Model: Semiconductor Stack Revenue
Early revenue comes from paid evaluations and development systems; long-term value comes from chips, software, and IP licensing.
| Revenue Line | Description |
|---|---|
| Design partnerships / NRE | Paid workload integration |
| Development systems | Cards, appliances, reference platforms |
| LFP chips + modules | Fabless semiconductor sales |
| IP + chiplet licensing | Upfront license + royalty |
| SDK + enterprise support | Subscriptions and support |
Fabless: outsourced fabrication, packaging, and test — software and IP grow margin over time.
Competition: Win on Workload Economics
LFP does not need to beat every accelerator on every benchmark. It must dominate workloads where watts, cooling, autonomy, or latency drive the buying decision.
Illustrative positioning — win where watts and milliseconds matter
| Technology | Architecture Maturity | Energy / Location Advantage |
|---|---|---|
| GPUs | High | Low |
| TPUs / Cloud ASICs | High | Low |
| Edge NPUs | High | High |
| FPGAs | Low | High |
| Neuromorphic | Low | High |
| LFP Target | High (target) | High |
J4 Differentiation
Different learning model · purpose-built hardware · edge-to-data-center path · software + IP moat
Sources: public docs for TPU, AWS accelerators, Loihi 2.
IP and Defensibility
Protect the learning method, the processor architecture, and the software ecosystem that makes the architecture usable. The underlying IP is held by J4.AI; Marziani Labs’ role under the partnership is commercialization and capital formation.
Published Patent Application
WO2024258795A1
US20240419998A1
LFP Instruction Set + Processing Elements
Core architecture protection
SPDE Assembly Fabric + Pruning Hardware
Core architecture protection
Compiler, Runtime, Profiler, SDK
Software ecosystem
Benchmarks, Workload Corpus, Customer Co-Design
Applied know-how
Trade Secrets + Implementation Know-How
Applied know-how
Source: Google Patents. Legal status must be confirmed by patent counsel.
Traction: Foundation Complete, Proof Ahead
The core architecture is documented. The next stage converts internal results into independent, investor-grade evidence.
Validation, not just theory
Today
Published patent application · software implementation · energy reductions on selected computations · defined LFP processor concept · applied AI engagements reported across financial trading, media & entertainment, and energy · new video-gaming industry customer (2026)
Next Proof Points
Reproducible benchmark suite · independent energy and accuracy validation · FPGA kernels and scale-out model · 3–5 paid design partners · first LFP silicon
Sixteen years of continuous operation. The strongest traction argument is not a benchmark but a runtime. J4 completed its prototype in 2010 and reports having run the resulting system continuously since — a machine the company describes as an artificial superintelligence, doing production work rather than sitting in a lab.
The most legible proof of that is the market work. Live tick data is an unforgiving environment: the data arrives at a fixed rate whether or not the computation keeps up. J4’s progression from one prediction per day in 2015 to calculation at tick rate today is the efficiency claim demonstrated under a clock it does not control (Section 07).
Research frontier: alongside the LFP, J4.AI reports preliminary results on combinatorial optimization and is working to carry them to conclusion — a second commercial line and the second gate on the brain-scale roadmap. See Section 10.
Benchmarking note: MLCommons benchmark principles.
Team: Operating Company in Place; Silicon Team to Build
The financing should assemble the semiconductor execution team around the inventor and core architecture, alongside Marziani Labs’ role in platform commercialization and capital formation under the partnership.
Jeff Glickman
Founder + inventor, J4.AI · 50 years working on AI · foundational ML patents · core learning method · technical vision + IP
Silicon Leadership
Chief silicon architect · RTL + verification · physical design + packaging
Platform Business
Compiler/runtime · BD + design partners · finance, IP, operations
The operating team is in place. The financing hires silicon; it does not hire a company. J4’s executive bench is already staffed.
| J4.AI Leadership | Background |
|---|---|
| Jeff Glickman Founder & Inventor | University of Illinois Urbana-Champaign under John Bardeen · five decades split roughly evenly between defense and commercial work · approximately 50 patents, including foundational patents underlying modern machine learning · software deployed aboard the International Space Station and in defense systems · invited lecturer at MIT CSAIL · began teaching semiconductor physics at 16 |
| David Oring Chief Operating Officer | Lehigh engineering, Columbia MBA · career on Wall Street across Donaldson, Lufkin & Jenrette, Bear Stearns, and KBW · managed hedge funds of roughly $300M · co-founded a registered investment advisor and grew it from under $2M to just under $1B across some 400 separately managed accounts, running compliance, trading, operations, and the technology stack |
| Kevin Jernigan Chief Product Officer | Computer science at Harvard · ten years at Oracle across two tenures · five years at AWS, then MongoDB and Google Cloud, on product teams throughout · database and AI specialization · joined J4 in 2025 |
| Rob Emanuele Director of Engineering | Computer scientist · began in telecom and datacom at Bell Labs · built network and server systems for large-scale multiplayer games · distributed-systems roles at Ask.com, Bloglines, and Rackspace · worked on the Microsoft settlements at the Department of Justice |
Glickman trained at the University of Illinois Urbana-Champaign under John Bardeen — the only person to win the Nobel Prize in Physics twice, for the transistor and for the theory of superconductivity. He began with the Office of Naval Research in the mid-1970s and has split a five-decade career between government contract work and the commercial-industrial sector; the first course he taught was semiconductor physics, including Josephson junctions — a foundation of today’s quantum hardware.
Source: inventor listed on Google Patents.
36-Month Plan: Retire the Big Risks First
The funding plan is structured to validate the method before committing the largest silicon dollars.
Key questions retired along the way: Does the algorithm generalize? Does the energy advantage survive memory/data movement? Does the compiler map workloads efficiently? Do customers adopt a new learning model?
Illustrative Financial Model
A fabless model can move from NRE and development systems to silicon, software, support, and licensing revenue.
| Management Case ($M) | Y1 | Y2 | Y3 | Y4 | Y5 |
|---|---|---|---|---|---|
| Revenue | $0 | $8 | $60 | $260 | $650 |
| Gross margin | — | 25% | 48% | 60% | 64% |
| EBITDA | ($39) | ($46) | ($35) | $61 | $266 |
Illustrative management targets; not audited forecasts.
Funding Request: $150 Million
The financing is intended to deliver independent validation, first LFP silicon, development systems, and commercial customer pilots — structured as a recommended milestone-based build.
Two financings, two horizons. The $150M silicon program runs alongside a smaller near-term raise that commercializes what already works. The $150M is not a single up-front requirement — it is gated to performance benchmarks and released against them, so capital follows proof rather than preceding it.
| Track | Purpose | Horizon |
|---|---|---|
| $10M Commercialization | Two halves. First: take the stochastic learning already running in production, expose it on RESTful endpoints, and make it publicly available as a revenue-generating service. Second: carry the combinatorial optimization work to completion and publish it as a commercial API for logistics, routing, and scheduling (Section 10). | Near term · revenue-generating · funds operations |
| $150M Silicon | The Logic Field Processor platform — independent validation, FPGA scale-out, RTL, tape-out, first silicon, SDK, and customer pilots. Milestone-gated and released in tranches against benchmark performance. | 36 months · platform build |
The two tracks are complementary rather than sequential. The commercialization track converts existing capability into cash flow and market evidence; the silicon track builds the processor that changes the economics of the method permanently. Use of funds below refers to the $150M silicon program.
| Use of Funds | Amount |
|---|---|
| Silicon architecture / RTL / verification | $45M |
| EDA, IP, foundry, tape-out, packaging NRE | $30M |
| Compiler, runtime, SDK, simulator | $25M |
| FPGA, first-silicon bring-up, dev systems | $15M |
| Design partners, pilots, BD, market entry | $12M |
| IP, security, compliance, legal | $8M |
| Working capital + contingency | $15M |
Recommended Tranche Structure
$35M initial close · $65M validation tranche · $35M tape-out tranche · $15M production reserve
Generative AI cannot scale indefinitely by adding more power, more water, and more distance.
Stochastic Learning
The method
Logic Field Processor
The machine
$150M Financing
The platform build
Massive intelligence — wherever it is needed.
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